The present invention is directed to integrated circuits and their processing for the manufacture of electronic devices. More particularly, the invention provides a method for manufacturing a capacitor structure for a liquid crystal on silicon (“LCOS”) device for displays. But it would be recognized that the invention has a much broader range of applicability.
Electronic display technologies have rapidly developed over the years. From the early days, cathode ray tube technology, commonly called CRTs, outputted selected pixel elements onto a glass screen in conventional television sets. These television sets originally output black and white moving pictures. Color television sets soon replaced most if not all black and white television units. Although very successful, CRTs were often bulky, difficult to make larger, and had other limitations.
CRTs were soon replaced, at least in part, with liquid crystal panel displays. These liquid crystal panel displays commonly called LCDs used an array of transistor elements coupled to a liquid crystal material and color filter to output moving pictures in color. Many computer terminals and smaller display devices often relied upon LCDs to output video, text, and other visual features. Unfortunately, liquid crystal panels often had low yields and were difficult to scale up to larger sizes. These LCDs were often unsuitable for larger displays often required for television sets and the like.
Accordingly, projection display units have been developed. These projection display units include, among others, a counterpart liquid crystal display, which outputs light from selected pixel elements through a lens to a larger display to create moving pictures, text, and other visual images. Another technology is called “Digital Light Processing” (DLP), which is a commercial name from Texas Instruments Incorporated (TI) of Texas, USA. DLP is often referred to as the use of “micro-mirrors.” DLP relies upon a few hundred thousand tiny mirrors, which line up in 800 rows of 600 mirrors each. Each of the mirrors is hinged. An actuator is attached to each of the hinges. The actuator is often electrostatic energy that can tilt each of the mirrors at high frequency. The moving mirrors can modulate light, which can be transmitted through a lens and then displayed on a screen. Although DLP has been successful, it is often difficult to manufacture and subject to low yields, etc.
Yet another technique is called LCOS, which uses both mirrors and liquid crystals. LCOS uses liquid crystals applied to a reflective mirror substrate. As the liquid crystals “open” or “close,” light is reflected or blocked, which modulates the light to create an image for display. Often times, there are at least three LCOS chips, each corresponding to light in red, green, and blue channels. LCOS, however, has many limitations. As merely an example, LCOS is often difficult to manufacture. Additionally, LCOS requires at least the three chips that make the projector bulky and heavy and leads to high costs. Accordingly, LCOS has not been adapted to portable projectors.
From the above, it is seen that an improved technique for processing devices is desired.
BRIEF SUMMARY OF THE INVENTION
According to the present invention, techniques for processing integrated circuits for the manufacture of electronic devices are provided. More particularly, the invention provides a method for manufacturing a capacitor structure for a liquid crystal on silicon (“LCOS”) device for displays. But it would be recognized that the invention has a much broader range of applicability.
As additional background information, a conventional LCOS backplane CMOS driver usually employs at least the following components in a unit display pixel (See FIG. 1):
1) a high voltage (HV) MOS selector transistor 101, which includes a row 105, column 103, and output 107;
2) a polysilicon insulator polysilicon (PIP) capacitor, which includes electrodes 115, 112, which is coupled to ground 117 and line 111 respectively;
3) an aluminum top metal electrode 109 also as a reflector to incident light; and
4) a subsequent metal light shield to the top metal electrode (TM);
each of these components, taking one or two mask layers of photo/etch processing, operates individually for its assigned but limited functionality. Meanwhile, as the aluminum (Al) top metal becomes even thinner for better reflectivity , it is less feasible to use the top metal for bonding pads. An extra passivation etch is often required to open the bonding pads down to a thicker subsequently lower metal layer for chip bonding. To further increase the performance versus cost ratio, an improvement in the efficiency in comprehensively utilizing the limited layer stack and improving, and even maximizing the performance of an LCOS backplane driver chip is desirable. These and other limitations have been overcome, at least in part and/or whole, by embodiments of the present invention.
In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer.
In an alternative specific embodiment, the present invention provides an alternative LCOS device. The device has a semiconductor substrate, e.g., silicon wafer. The device has a high voltage MOS transistor formed within the semiconductor substrate. Preferably, the high voltage MOS transistor has a first source/drain coupled to a first node, a second source/drain coupled to a second node, and a gate coupled to a row node. A PIP capacitor structure is coupled to the HV MOS transistor. Preferably, the PIP capacitor structure has a first polysilicon layer coupled to the second node of the HV MOS transistor, a first capacitor insulating layer overlying the first polysilicon layer, and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground potential. A MIM capacitor structure is coupled to the HV MOS transistor. Preferably, the MIM capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the HV MOS transistor. A pixel electrode comprises the first metal layer. Preferably, the pixel electrode is coupled to the second node of the HV MOS transistor. A mirror surface is on the pixel electrode. A light shielding layer is formed from a portion of the second metal layer and a ground potential is coupled to the reference potential. Preferably, the HV MOS device is adapted to switch a voltage potential of about 10 volts to about 20 volts.
In yet an alternative specific embodiment, the invention provides a method for fabricating an LCOS device. The method includes providing a semiconductor substrate. The method also includes forming a transistor structure within the semiconductor substrate. The transistor structure has a first node, a second node, and a row node. The method includes forming a first capacitor structure coupled to the transistor structure. Preferably, the first capacitor structure comprises a first polysilicon layer coupled to the second node of the transistor structure, a first capacitor insulating layer overlying the first polysilicon layer, and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential. The method further includes forming a second capacitor structure coupled to the transistor structure. Preferably, the second capacitor structure comprises a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor structure. The method includes forming a pixel electrode comprising the first metal layer. Preferably, the pixel electrode is coupled to the second node of the transistor structure. The method includes forming a mirror surface on the pixel electrode and forming a light shielding layer from a portion of the second metal layer.
Many benefits are achieved by way of the present invention over conventional techniques. For example, the present technique provides an easy to use process that relies upon conventional technology. In some embodiments, the method provides higher device yields in dies per wafer. Additionally, the method provides a process that is compatible with conventional process technology without substantial modifications to conventional equipment and processes. Preferably, the invention provides for an improved capacitor structure for LCOS devices used for displays. Such capacitor structure uses multiple capacitor structures according to preferred embodiments. Certain embodiments of the present invention may include one or more of the following features:    1) The unit display pixel has a high voltage (HV) MOS select transistor with its drain electrically connected to an MIM capacitor and a PIP capacitor in parallel;    2) The MIM capacitor has a top metal (TM) pixel electrode also as a light reflector and the grounded subsequent metal light-shield, separated by a thin layer of dielectric material such as Si3N4, SiO2 or Al2O3, or any combination of these and other suitable materials;    3) The PIP capacitor has a top polysilicon plate and bottom polysilicon plate, also separated by a thin layer of dielectric material such as Si3N4, SiO2 or Al2O3 or in combination of these and other suitable materials; and    4) A thin but wide open via connects the TM and the subsequent metal layer at a bonding pad region to form a stacked, thicker bond pad structure, more robust than a single (either TM or subsequent metal) layer bond pad; such a via does not need W plug CVD deposition as it is much thinner than convention IMD dielectric.
Depending upon the embodiment, the present invention in comprehension would expand while integrate feasible functionality of those noted features beyond their conventional settings and thus offer a much-improved value versus cost ratio. In particular, total capacitance built through both the PIP and MIM capacitors in electrically parallel connection on a unit pixel cell could be much increased while more real estate could be relocated to a higher driving current HV MOS transistor. And not only are the TM and the subsequent metal layer utilized for the array pixels' second capacitor, MIM capacitor but also integrated as a more robust bonding pad structure. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more throughout the present specification and more particularly below.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.